1. Field of the Invention.
The present invention relates to the transfer of data within a computer system from a relatively slow peripheral I/O device through a high speed data bus to a system memory.
2. Description of the Related Art.
Typical small computer systems incorporate a microprocessor, various kinds of memory, one or more buses, and a number of devices that transfer data over the buses between themselves, the memory and the microprocessor. A common configuration of computer system provides a central processing unit (CPU) such as a microprocessor coupled to a cache or other local memory and to a memory controller by a local processor bus. The memory controller is connected to the system memory over a memory bus and provides controlled access to the system memory for the microprocessor as well as for other devices in the computer system over the system bus of the computer system. Frequently, data communications between the microprocessor and other devices within the computer system are mediated by the system memory, so that the transfer of data from the various devices to the system memory is an important aspect of the operation of small computer systems. Data transfers between the system memory and other devices of the computer require that the system bus arbiter recognize the device request for a memory transaction and cause the microprocessor to relinquish control of the bus to the device for the memory transaction. The system bus may have different configurations, but is typically a high speed, synchronous bus having a configuration and architecture like that of the peripheral component interface (PCI) bus. A particular implementation of such a small computer system having a PCI bus and which illustrates a variety of conventional aspects of data transfers, including bus control and arbitration, is described in U.S. Pat. No. 5,450,551 to Amini, et al., which is hereby incorporated by reference.
The PCI bus architecture places significant restrictions on the types of devices that can couple to the bus. Devices connected to the PCI bus generally should be, for example, thirty-two bit devices that have bus mastering capabilities. Examples of such devices include Winchester-type hard disk drives and graphics controllers. Such bus mastering devices include internally the registers and logic required for performing direct memory access (DMA) and so need not rely on the bus mastering capabilities of a system DMA. Present day small computer systems also incorporate comparatively slow peripheral I/O devices that must perform transactions with the memory but which cannot be directly interfaced to the PCI or other system bus of the computer system. These PCI incompatible devices operate at slower data rates than the PCI bus and do not have the bus mastering capabilities required for direct connection to the PCI bus. Examples of PCI incompatible devices include controllers for floppy disk drives as well as other I/O devices like parallel ports and infrared data ports.
It has generally been necessary to provide a separate I/O bus, such as an ISA bus, in addition to the PCI bus within the computer system to be shared by the lower speed I/O devices that cannot directly couple to the PCI bus. The devices coupled to the ISA bus are separated from the system PCI bus by a bus bridge, which preferably includes a DMA controller to control the memory I/O (storage and reading) transactions between the devices connected to the ISA bus and the system memory over the PCI bus. A conventional configuration of a DMA system for coupling peripheral I/O devices on an ISA bus to a PCI system bus is shown in FIG. 1. Various peripheral I/O devices, collectively indicated by 10 in FIG. 1, are coupled to the ISA bus 20 via a standard bus bridge 30 to the PCI system bus 40. The peripheral I/O devices may include, for example, a floppy disk controller 12, a parallel port controller 14 and an infrared port controller 16. Other peripheral devices might also be provided. Access to the shared ISA bus 20 by the various peripheral I/O devices 10 is controlled by the DMA controller 32, which is provided along with a buffer memory 34 on the standard I/O bridge 30 coupled between the ISA bus 20 and PCI bus 40. Conventionally, the DMA controller includes both the logic for arbitrating requests for bus access as well as the logic for communicating control signals for the bus transactions to the peripheral I/O devices.
Typically, the DMA controller 32 on the bridge 30 is of the 8237 type and includes eight thirty-two bit channels for transferring data. When one of the I/O devices 10 wishes to gain access through the PCI bus 40 to the system memory, or otherwise to access the PCI bus 40, the I/O device 10 issues a DMA request (DREQ) to the DMA controller 32. The DMA controller 32 issues a request to the PCI bus arbiter for bus access. When the DMA controller 32 is granted control of the bus, the DMA controller 32 signals (DACK) the appropriate I/O device 10 and initiates a transfer of data from the I/O device 10 through the ISA bus 20 and through the bridge 30 to the PCI bus 40. The PCI bus provides the data to its destination, for example, to a memory controller for storage in the system memory or to another device connected to the PCI bus 40 (neither shown).
The particular order of transactions described here may proceed in a slightly different manner to accommodate both the slow nature of the I/O devices 10, and also to accommodate the very different speeds and protocols on the ISA bus 20 and the PCI bus 40. Often, a buffer memory 34 is provided on the bridge to temporarily store the data that is being transferred from the PCI bus 40 to the I/O devices 10 and also to temporarily store the data that is being transferred from the active one of the I/O devices 10 over the ISA bus 20, through the bridge 30 and onto the PCI bus 40. Thus, the buffer memory 34 may be filled, under the direction of the DMA controller 32, during a data transfer operation from the system memory over the PCI bus 40 to the target one of the I/O devices 10. This is due to the PCI bus providing data to the buffer memory 34 at a much faster rate than the data can be transferred from the buffer 34 over the ISA bus 20 to the I/O devices 10.
For the transfer of data from the system bus to the peripheral I/O device, the simple description of DMA control set forth above may be practiced without reducing the performance of the computer system. The transfer of data from the I/O device 10 to the system memory over the PCI bus 40, however, can be further optimized from the basic DMA control sequence describe above to improve the performance of the computer system. In particular, the order of control signals might be varied from the described ordering of operations, or at least some delays might be inserted between some operations, to provide better system performance. To this end, the peripheral I/O device 10 might issue a DMA request to the DMA controller 32, which might not immediately issue a request for bus control. It might instead be preferred for the DMA controller to delay issuing a request for the bus until after the I/O device has transferred to the buffer memory 34 all of the data to be transferred, or at least a sufficient quantity of data to fill the buffer memory, before the DMA controller 32 issues a request to the PCI bus arbiter for bus control. This strategy will reduce the amount of time dedicated by the PCI bus to waiting for data from the I/O device. Thus, one function of the bridge in the FIG. 1 system is to provide improved device performance by providing a buffer to equilibrate the speeds of the PCI and ISA buses. Another function of the bridge 30 is to accommodate and translate between the different protocols and timings of the PCI and ISA buses.
The transfer of data between the system memory and slow peripheral I/O devices is a source of performance and reliability problems in small computer systems, since most of the computer system operates at a much higher data rate than these peripheral devices. The architecture described above places all of the peripheral I/O devices on a shared data bus and conducts DMA operations completely and in sequence. This means that peripheral I/O devices that have comparatively high data transfer rates occasionally will be queued behind slower peripheral I/O devices awaiting a DMA transaction, substantially negating the advantage of the higher data transfer rates. It would is desirable to provide a system in which higher speed peripheral I/O devices can better avoid delays caused by DMA transactions involving slower peripheral I/O devices. Conventional methods of interfacing slow peripheral I/O devices to the host computer system are further undesirable as requiring space on the system motherboard to provide a generally incompatible and obsolete shared I/O bus.